Quick Links

LMS Syllabus All Notes Class Library
Past Lesson Note

This note is from 7 months ago. You're viewing content from a previous lesson.

Daily Note for October 27, 2025 Past Lesson

  1. Welcome back from October break. What did you do?

  2. Since it's been a bit, we are going to review:
    1. A1.1.5 Describe the fetch, decode and execute cycle.
      1. The basic operations a CPU performs to execute a single instruction in machine language
      2. The interaction between memory and registers via the three buses: address, data, control
    2. A1.1.4 Explain the purposes of different types of primary memory.
      • Random-access memory (RAM), read only memory (ROM), cache (L1, L2, L3), registers
      • The interaction of the CPU with different types of memory to optimize performance
      • The relevance of the terms “cache miss” and “cache hit”
    3. A1.1.1 Describe the functions and interactions of the main CPU components.
      • Units: arithmetic logic unit (ALU), control unit (CU)
      • Registers: instruction register (IR), program counter (PC), memory address register (MAR), memory data
      register (MDR), accumulator (AC)
      • Buses: address, data, control
      • Processors: single core processor, multi-core processor, co-processors
      • A diagrammatic representation of the relationship between the specified CPU components
    4. A1.1.2 Describe the role of a GPU.
      • The architecture that allows graphics processing units (GPUs) to handle specific tasks and makes them
      suitable for complex computations
      • Real-world scenarios may include video games, artificial intelligence (AI), large simulations and other
      applications that require graphics rendering and machine learning.
    5. A1.1.3 Explain the differences between the CPU and the GPU. (HL only)
      • Differences in their design philosophies, usage scenarios
      • Differences in their core architecture, processing power, memory access, power efficiency
      • CPUs and GPUs working together: task division, data sharing, coordinating execution

  3. Please write this 3 question "assessement for learning" quiz.

  4. We will choose a test date (A1.1.1 to A1.1.6)

  5. We will learn about: 

    1. A1.1.6 Describe the process of pipelining in multi-core architectures. (HL only)
      • The instructions fetch, decode, execute
      • Write-back stages to improve the overall system performance in multi-core architectures
      • Overview of how cores in multi-core processors work independently and in parallel