Past Lesson Note

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Daily Note for October 14, 2025 Past Lesson

 
• Random-access memory (RAM), read only memory (ROM), cache (L1, L2, L3), registers
• The interaction of the CPU with different types of memory to optimize performance
• The relevance of the terms “cache miss” and “cache hit”
 
  1. With headphones, please watch this video: https://drive.google.com/file/d/1LkTCnHecwpHV0a3AO4Tlzo_Og731yjZ-/view?usp=sharing

    1. I made a mistake in the video; the ALU is NOT a register. 

  2. Please review these slides: https://docs.google.com/presentation/d/19e7fpj9G3S57UZJK-0HcRBP8vKmxflH5PkJ72GneaaU/edit?usp=sharing

  3. The answers to these four questions are due by the start of next class: 
    1. Outline why can’t we use only registers or cache for all memory.

    2. Outline how do cache hits/misses affect performance.

    3. Describe what happens when the CPU runs out of cache space.

    4. Explain how RAM and ROM differ in usage and design.